The present invention relates to a watchdog circuit for monitoring the function of a processor, in which the processor outputs a cyclically repeating test signal to the watchdog circuit, and the watchdog circuit generates a reset signal for the processor if the test signal does not appear in a time slot specified by the watchdog circuit.
This kind of slot watchdog is described for instance in DE 33 20 587 A1 or EP 0 479 806 B1. From these references it is known to use watchdog circuits, for instance for microprocessors that monitor the processor program sequence. If the program sequence is correct, the microprocessor at certain time intervals triggers the watchdog circuit with a test signal. If this test signal appears in the time slots specified by the watchdog circuit, then the program sequence of the microprocessor is continued unhindered. If an error occurs in the microprocessor, however, for instance as a result of interruption of the program sequence, then the microprocessor does not send its test signal to the watchdog circuit within the specified time slot. This causes the watchdog circuit to output a reset signal, which resets the microprocessor to the program start and/or signals an error function of the microprocessor.
From Elektronik, Vol. 38, No. 4, Feb. 17, 1988, pages 48 to 51 and 54 through 56, a watchdog circuit is known whose time slot is variable in width, so that the monitoring periods for the connecting processor can be adapted to the applicable program portion or processor operating mode (transfer mode, hold mode, read mode, or standby mode).
In accordance with the present invention, the time slot specified by the watchdog circuit, within which the test signal of the processor to be monitored should appear, is controllable in its width. Expediently, the time slot is widened precisely in the starting phase of the program sequence of the processor. Experience teaches that the microprocessor, in the starting phase of its program sequence, does not yet reach the desired exact time matrix for the test signal, and so if a narrow time slot is specified the watchdog circuit signals an error function in the program sequence more often to the processor, by outputting a reset signal. Restarting of the program sequence would then occur more often, even though actually there is no error function in the program sequence. By widening the time slot in the watchdog circuit, greater play for starting up is given to the program sequence in the starting phase. As soon as the starting phase is finished and the program sequence has reached its steady state, the time slot is returned to its original width again. For varying the width of the time slot, only its upper limit needs to be controllable.